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paroli? is a registered trademark of infineon technologies ag fiber optics may 2000 v23814-k1306-m230 parallel optical link: paroli? tx dc/mux-enc V23815-K1306-M230 parallel optical link: paroli? rx dc/demux-dec features power supply (3.3 v) low voltage differential signal electrical interface (lvds) 22 electrical data + 1 clock channels low skew, bit parallel transmission interface to sci and hippi 6400 standard 12 optical data channels electrical transmission data rate of 150-500 mbit/s per channel, total link data rate up to 11 gbit/s two clocking modes can be selected (sci/strobe) transmission distance up to 75 m at maximum data rate 850 nm vcsel array technology pin diode array technology 62.5 m graded index multimode fiber ribbon mt based optical port smd technology class 1 fda and class 3a iec laser safety compliant fc open fiber control (ofc) interface supported (to con- figure a class 1 iec laser safety compliant system) applications telecommunication switching equipment access network data communication interframe (rack-to-rack) intraframe (board-to-board) on board (optical backplane) absolute maximum ratings stress beyond the values stated below may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. supply voltage (v cc ?v ee ).................................... ?0.3 v to 4.5 v data/control input levels (v in ) (1) ................ ?0.5 v to v cc +0.5 v lvds input differential voltage ( |v id | ) (2) .............................. 2.0 v operating case temperature (t case ) (3) ...............0c to 80c storage ambient temperature (t stg )................ ?20c to 100c operating moisture ............................................... 20% to 85% storage moisture.................................................... 20% to 85% soldering conditions temp/time (t sold, t sold ) (4) ....260c/10s esd resistance (all pins to v ee human body model) (5) ....... 1 kv notes 1. a t lv d s a n d lvc m o s i n p u t s . 2. |v id |=|(input voltage of non-inverted input minus input voltage of inverted input)|. 3. measured at case temperature reference point (see dimensional drawing, figure 13 on page 12). 4. hot bar or hot air soldering. 5. to avoid electrostatic damage, handling cautions similar to those used for mos devices must be observed.
fiber optics v23814/15-k1306-m230 parallel optical link: paroli? tx/rx dc 2 description paroli is a parallel optical link for high-speed data transmis- sion. a complete paroli system consists of a transmitter module, a 12-channel fiber optic cable, and a receiver module. transmitter v23814-k1306-m230 the paroli transmitter module converts parallel electrical input signals (data and clock) into parallel optical output signals. figure 1. transmitter block diagram all electrical data and clock inputs are lvds compatible. the module also features several lvcmos compatible control inputs and outputs, which are described in the transmitter pin description (table starting on page 5). the module features multiplexing and encoding of 22 electrical data input channels to 11 optical data output channels. the input data are serialized by 2 to 1 multiplexers which results in a reduced data rate at the electrical interface. the multiplexed data are encoded (4b/5b encoding) to achieve dc-balanced sig- nals at the input of the laser driver. the electrical input clock signal is used to control an integrated pll circuit, which generates internal clock signals for encoding and multiplexing. the pll circuit also generates a frame signal for the optical interface, which is transmitted over a separate fiber. transmission delay of the paroli system is at a maximum of 4 strobe cycles + 3 ns for the transmitter, 3 strobe cycles + 3 ns for the receiver, and approximately 5 ns per meter for the fiber optic cable. clocking modes the transmitter can be operated in one of two input clocking modes: strobe mode or sci mode. the mode is selected via clk_sel input. in strobe mode, the rising edges of the non- inverted clock signal are centered over the data bits. in sci mode, high/low transitions of clock and data signals coincide. in sci mode, the transmitter?s electrical interface complies with the sci standard. see timing diagram figure 5 on page 4. multiplexing and encoding the electrical input data are strobed into the input register with the internal clock signal generated by the pll and then multi- plexed 2:1. input channels 1 to 11 are grouped with input chan- nels 12 to 22, i.e. data inputs 1 and 12 feed optical data output 1; data inputs 2 and 13 feed optical data output 2, etc. four data bits read from two input channels during two strobe cycles form 4b words. inside the 4b word, data from the lower inputs (1 to 11) is transmitted first, i.e. after input data are strobed. inputs 1 to 11 are routed before inputs 12 to 22. 4b words are then fed through eleven separate 4b/5b encoders to form the signals to be transmitted over the optical interface. coding is based on the running disparity of previously transmit- ted output data. with a running disparity 0, either more high than low levels or an equal number of highs and lows have been transmitted. the next output nibble will be inverted if high levels again dominate; otherwise it will be sent without inver- sion. with a running disparity <0, more low than high levels have been transmitted. the next output nibble will be inverted if low levels again dominate; otherwise it will be sent uninverted. to indicate whether a nibble has been inverted, an inversion bit is added, thus forming a 5b word (high, if transmitted nibble is uninverted; low, if transmitted nibble is inverted). it is placed in front of the nibble (at the beginning of the 5b word) and imme- diately follows the frame transition. frame signal transitions delimit 5b words. each 5b word contains the inversion bit and the nibble (inverted or non-inverted) mounted from two input data strobe cycles. the 5b words and frame signal are the signals transmitted over the optical interface. the pulse lengths of the 5b word and the frame signal is twice the pulse length of the electrical input signal. example to transmit electrical data at the maximum data rate of 500 mbit/s per channel the corresponding clock signal (square 0101 pattern) has a frequency of 250 mhz in sci mode or 500 mhz in strobe mode. the frame signal with a corresponding fre- quency of 125 mhz is transmitted via fiber #1. the data rate of the optical signal at the transmitter output is 1.25 gbit/s in each of the fibers #2 to #12. laser safety the transmitter of the dc coupled parallel optical link (paroli) is an fda class 1 laser product. it complies with fda regula- tions 21 cfr 1040.10 and 1040.11. the transmitter is an iec class 3a laser product as defined by iec 60825-1. to avoid pos- sible exposure to hazardous levels of invisible radiation, do not exceed maximum ratings. the paroli module must be operated under the specified operating conditions (supply voltage between 3.0 v and 3.6 v, case temperature between 0c and 80c) under all circum- stances to ensure laser safety. caution do not stare into beam or view directly with optical instruments. the use of optical instruments with this product will increase eye hazard. note any modification of the module will be considered an act of ?manu- facturing,? and will require, under law, recertification of the product under fda (21 cfr 1040.10 (i)). figure 2. laser emission pll -reset clk_sel laser controller up module up data fibers frame fiber #1 clock input data inputs electrical inputs optical outputs le laser enable -le input stage multiplexer encoder laser driver vcsel array 22 22 11 11 11 frame laser aperture and beam
fiber optics v23814/15-k1306-m230 parallel optical link: paroli ? tx/rx dc 3 start-up procedure detailed information can be found in the data sheet of the paroli test board ac/dc, part number v23814-s1306-m931 and v23815-s1306-m931. switch system power supply on and hold -reset at low level release -reset when v cc has reached 3.0 v level and clock input is stable delay 100 ms until laser controller and pll have settled after 100 ms mu and lcu will be high apply data input module starts transmitting. le/-le can be used to activate/deactivate laser output at any time. for data transmission they must be activated. if the le and -le module pins are not connected, then laser output is automatically activated. technical data the electro-optical characteristics described in the following tables are valid only for operation under the recommended operating conditions. recommended operating conditions notes voltages refer to v ee =0 v. 1. noise frequency is 1 khz to 10 mhz. voltage is peak-to-peak value. 2. noise frequency is > 10 mhz. voltage is peak-to-peak value. 3. level diagram figure 3. input level diagram 4. |v id |= | (input voltage of non-inverted input minus input voltage of inverted input) |. 5. 20% - 80% level. 6. measured between 0.8 v and 2.0 v. 7. lower limit of clock frequency due to pll frequency limitations. 8. measured at 50% level. 9. the unit interval ui refers to a strobe cycle in this case. 1 ui = 1/f clock in strobe mode and 1 ui = 1/(2 f clock ) in sci mode parameter symbol min. max. units power supply voltage v cc 3.0 3.6 v noise on power supply (1) n ps1 50 mv noise on power supply (2) n ps2 100 lvds input voltage range (3) v lvdsi 500 1900 lvds input differential voltage (3, 4) |v id | 100 1000 lvds clock input rise/fall time (5) t r , t f 100 400 ps lvcmos input high voltage v lvcmosih 2.0 v cc v lvcmos input low voltage v lvcmosil v ee 0.8 lvcmos input rise/ fall time (6) t r , t f 20 ns clock input frequency, sci mode (7) f clock 75 250 mhz clock input frequency, strobe mode (7) f clock 150 500 mhz clock input duty cycle distortion dcd 45 55 % input skew between clock inputs (8) t spn 0.75 x t r , t f ps clock input total jitter (pk-pk)(9) cj 0.1 ui mv 1900 500 time |v id |
fiber optics v23814/15-k1306-m230 parallel optical link: paroli ? tx/rx dc 4 transmitter electro-optical characteristics notes 1. data rate on electrical channel. number of consecutive high or low bits is unlimited. 2. figure 4. lvds input stage 3. source current 4. sink current notes optical parameters valid for each channel. 1. 20% ? 80% level, measured using a gbe (gigabit ethernet) filter. 2. measured with 01010... (square) optical output pattern and in mod- ule thermal steady state status. without cooling this steady state status is reached after approximately 10 minutes. figure 5. timing diagrams strobe mode note 1. refers to positive clock input signal. see measurement conventions (figure 6). parameter symbol min. typ. max. units supply current l cc 1100 1300 ma power consump- tion p3.64.7w data rate in sci mode (1) d rsci 150 500 mbit/s data rate in strobe mode (1) d rstr lvds differential input impedance (2) r in 80 120 ? lvcmos output voltage low v lvcmosol 0.4 v lvcmos output voltage high v lvcmosoh 2.5 lvcmos input current high/low i lvcmosi ? 500 500 a lvcmos output current high (3) i lvcmosoh 0.5 ma lvcmos output current low (4) i lvcmosol 4.0 lvds differential input current |i i |5.0 1.2 v 0.2 v r in /2 r in /2 v cc c data in p data in n 14 k ? 8 k ? parameter symbol min. max. units optical rise time (1) t r 400 ps optical fall time (1) t f random jitter (14 ) (2) j r 0.26 ui deterministic jitter j d 0.17 launched average power p avg ? 11 ? 6.0 dbm launched power shutdown p sd ? 30 center wavelength c 820 860 nm spectral width (fwhm) ? 2.0 spectral width (rms) ? 0.85 relative intensity noise rin ? 116 db/hz extinction ratio (dynamic) er 5.0 db parameter symbol min. typ. max. units input setup time (1) t 1 250 ps input hold time (1) t 2 t 1 t 2 data in 1...22 clock out p n |v id | min.
fiber optics v23814/15-k1306-m230 parallel optical link: paroli ? tx/rx dc 5 sci mode . maximum input skew=(2*data rate) ? 1 ? 250 ps ? dcd in-clock where dcd in-clock = | (data rate) ? 1 ? dcd*( 1 / 2 data rate) ? 1 | (dcd: see recommended operating conditions). note 1. see measurement conventions (figure 6). reset timing diagram notes 1. valid after the release of -reset. (clock input must first be stable. keep -reset low until clock input is at stable frequency.) 2. only when not used as power-on reset (see start-up procedure for power-on reset). at any failure recovery, -reset should be brought to low level for at least t 3 . figure 6. measurement conventions for lvds signals setup and hold times setup and hold times are measured between the cross point of positive and negative clock and the points where rising and falling data edge cross the borders of the v-range. figure 7. numbering conventions transmitter the numbering conventions for the tx and rx modules are the same. transmitter pin description parameter symbol min. typ. max. units input skew (1) t s ps parameter symbol min. typ. max. units -reset on delay time (1) t 1 100 ms -reset off delay time t 2 50 s -reset low duration (2) t 3 100 s t s t s data out 1...22 clock out p n |v id | min. 3.6 v v cc data 3.0 v data invalid data valid 0.8 v t 3 t 2 t 1 3.6 v v cc data -reset 3.0 v data invalid data valid 2.0 v t 3 t 2 t 1 t setup t hold data clock p n |v id | min. pin# pin name level/logic description 1v cc1 power supply voltage of laser driver 2 t.b.l.o. to be left open 3 4 5 6 lcu lvcmos out laser controller up high=laser controller is operational low=laser fault condition if -reset is high and v cc is > 3.0 v 7v ee ground 8v ee ground 9v cc3 power supply voltage of digi- tal circuitry and pll 10 mu lvcmos out module up high=normal operation low=laser fault or pll not locked or -reset low 11 cin lvds in clock input, inverted 12 cip lvds in clock input, non-inverted 13 di01n lvds in data input #1, inverted 14 di01p lvds in data input #1, non-inverted 15 di12n lvds in data input #12, inverted 16 di12p lvds in data input #12, non-inverted 17 di02n lvds in data input #2, inverted 18 di02p lvds in data input #2, non-inverted 19 di13n lvds in data input #13, inverted 20 di13p lvds in data input #13, non-inverted 21 di03n lvds in data input #3, inverted 22 di03p lvds in data input #3, non-inverted 23 di14n lvds in data input #14, inverted 24 di14p lvds in data input #14, non-inverted 25 v cc3 power supply voltage of digi- tal circuitry and pll 26 di04n lvds in data input #4, inverted 27 di04p lvds in data input #4, non-inverted 28 v ee ground 29 di15n lvds in data input #15, inverted 30 di15p lvds in data input #15, non-inverted
fiber optics v23814/15-k1306-m230 parallel optical link: paroli ? tx/rx dc 6 31 di05n lvds in data input #5, inverted 32 di05p lvds in data input #5, non-inverted 33 di16n lvds in data input #16, inverted 34 di16p lvds in data input #16, non-inverted 35 di06n lvds in data input #6, inverted 36 di06p lvds in data input #6, non-inverted 37 di17n lvds in data input #17, inverted 38 di17p lvds in data input #17, non-inverted 39 di07n lvds in data input #7, inverted 40 di07p lvds in data input #7, non-inverted 41 di18n lvds in data input #18, inverted 42 di18p lvds in data input #18, non-inverted 43 di08n lvds in data input #8, inverted 44 di08p lvds in data input #8, non-inverted 45 v ee ground 46 di19n lvds in data input #19, inverted 47 di19p lvds in data input #19, non-inverted 48 v cc3 power supply voltage of digi- tal circuitry and pll 49 di09n lvds in data input #9, inverted 50 di09p lvds in data input #9, non-inverted 51 di20n lvds in data input #20, inverted 52 di20p lvds in data input #20, non-inverted 53 di10n lvds in data input #10, inverted 54 di10p lvds in data input #10, non-inverted 55 di21n lvds in data input #21, inverted 56 di21p lvds in data input #21, non-inverted 57 di11n lvds in data input #11, inverted 58 di11p lvds in data input #11, non-inverted 59 di22n lvds in data input #22, inverted 60 di22p lvds in data input #22, non-inverted 61 clk-sel lvcmos in input clocking mode select high=strobe mode low=sci mode this input has an internal pull- up resistor. when left open, strobe mode is active. 62 t.b.l.o. to be left open 63 v cc3 power supply voltage of digi- tal circuitry and pll 64 -reset lvcmos in low active high=normal operation low=resets module, shuts laser diode array down this input has an internal pull- down resistor to ensure laser safety switch-off in case of unconnected -reset input. 65 v ee ground 66 v ee ground pin# pin name level/logic description 67 le lvcmos in laser enable. high=laser array is on if -le is also active. low=laser array is off. this input can be used for connec- tion with an open fiber con- trol (ofc) circuit to configure an iec class 1 link. this input has an internal pull-up, there- fore can be left open. 68 -le lvcmos in low active laser enable. low=laser array is on if le is also active. this input can be used for connection with an open fiber control (ofc) cir- cuit to configure an iec class 1 link. this input has an inter- nal pull-down, therefore can be left open. 69 t.b.l.o. to be left open 70 t.b.l.o. to be left open 71 t.b.l.o. to be left open 72 v cc1 power supply voltage of laser driver pin# pin name level/logic description
fiber optics v23814/15-k1306-m230 parallel optical link: paroli ? tx/rx dc 7 description receiver V23815-K1306-M230 the paroli receiver module converts parallel optical input signals (data and frame) into parallel electrical output signals. figure 8. receiver block diagram all electrical data and clock outputs are lvds compatible. the module also features several lvcmos compatible control inputs and outputs, which are described in the receiver pin description (table starting on page 10). the module features demultiplexing and decoding of 11 optical data input channels to 22 electrical data output channels. the frame signal is used to control an integrated pll circuit, which generates internal clock signals for decoding and demultiplex- ing. the pll circuit also generates a clock signal at the receiver output. transmission delay of the paroli system is at a maximum of 4 strobe cycles + 3 ns for the transmitter, 3 strobe cycles + 3 ns for the receiver, and approximately 5 ns per meter for the fiber optic cable. clocking modes the receiver can be operated in one of two output clocking modes: strobe mode or sci mode. the mode is selected via clk_sel input. in strobe mode, the rising edges of the non- inverted clock signal are centered over the data bits. in sci mode, high/low transitions of clock and data signals coincide. in sci mode the electrical interface complies with the sci stan- dard. see timing diagram figure 10. decoding and demultiplexing the input data received from the optical interface are strobed into the input register with the pll generated internal clock sig- nal. the data are read in relation to frame input. the input fre- quency expected at frame is one fifth of square input data frequency, as frame transitions indicate 5b word boundaries. frame input is expected to change levels simultaneously with data transitions. all eleven input data channels are fed through individual 5b/4b decoders. decoding is based on an inversion bit which is received at the first position of a 5b word. this bit determines whether the nibble received at bit positions 2, 3, 4 and 5 has to be inverted. an inversion bit high level indicates a nibble which was transmitted uninverted, i.e. this 4b nibble will be directly forwarded to the demultiplexer. if the inversion bit received is low, the corresponding nibble will be inverted by the decoder before it is demultiplexed. the 4b words from the decoders are then demultiplexed 1:2 to electrical output data channels. output channels 1 to 11 are grouped with output channels 12 to 22, i.e. optical data input 1 feeds electrical data outputs 1 and 12; optical data input 2 feeds electrical data outputs 2 and 13, etc. demultiplexing of a 4b word (with bits #1...#4) takes two data output cycles. during the first cycle, bit #1 is presented at the lower data out- put (1...11) and bit #2 at the higher data output (12...22). during the second cycle, bits #3 and #4 are presented at the lower and higher outputs, respectively. (example: of the 4b word from optical data channel 1, bit #1 is presented at corresponding lower data output 1 and bit #2 is presented at corresponding higher data output 12.) the demultiplexed data bits are presented as 22 parallel out- puts together with the output clock signal, the characteristics of which depend on the clocking mode. (see clocking modes above.) start-up procedure detailed information can be found in the data sheet of the paroli test board ac/dc, part number v23815-s1306-m931. switch system power supply on and hold -reset at low level release -reset when v cc has reached 3.0 v level wait for lock_det to become high module starts presenting data at the data outputs if oe is high. if oe is at a high level or left open during start-up, clock output will start running immediately after release of -reset. clock fre- quency will drift upwards to the operating frequency estab- lished by frame input when frame_det indicates sufficient input signal level. after pll has locked (indicated by lock_det high level) data outputs are also enabled. oe can be used for complete lvds switch-off whenever clock drift during start-up is critical. clk_sel -reset pll output stage decoder demulti- plexer ampli- fier pin diode array 11 11 22 11 22 ensd oe frame_det lock_det -sd11 data outputs clock output frame fiber data fibers optical inputs electrical outputs frame clock
fiber optics v23814/15-k1306-m230 parallel optical link: paroli ? tx/rx dc 8 technical data recommended operating conditions notes voltages refer to v ee =0 v. 1. noise frequency is 1 khz to 10 mhz. voltage is peak-to-peak value. 2. noise frequency is > 10 mhz. voltage is peak-to-peak value. 3. measured between 0.8 v and 2.0 v. 4. measured for all optical data channels with reference to the optical frame channel. a link operating distance of 75m at maximum data rate is supported when using a low skew fiber ribbon cable (skew specification < 1.2 ps/m, fiber bandwidth > 160 mhz km). longer link distances are supported at lower data rates. 5. 20% ? 80% level, measured using a gbe (gigabit ethernet) filter. receiver electro-optical characteristics notes .level diagram: figure 9. output level diagram 2. |v od |=|(output voltage of non-inverted output minus output voltage of inverted output)|. 3. v os = 1 / 2 (output voltage of inverted output + output voltage of non- inverted output). 4. lvds output must be differentially terminated with r t . 5. 20% - 80% level, measured with a maximum capacitive load of 5 pf. 6. source current. 7. sink current . parameter symbol min. max. units power supply voltage v cc 3.0 3.6 v noise on power supply (1) n ps1 50 mv noise on power supply (2) n ps2 100 differential lvds termination impedance r t 80 120 ? lvcmos input high voltage v lvcmosih 2.0 v cc v lvcmos input low voltage v lvcmosil v ee 0.8 lvcmos input rise/ fall time (3) t r , t f 20 ns optical frame input frequency f frame 37.5 125 mhz optical data, frame input skew (4) t si 0.2 ui optical data, frame input rise/fall time (5) t r , t f 400 ps optical data, frame input extinction ratio er 5.0 db input center wavelength c 820 860 nm parameter symbol min. typ. max. units supply current l cc 910 1030 ma power consumption p 3.0 3.7 w lvds output low voltage (1, 4) v lvdsol 925 mv lvds output high voltage (1, 4) v lvdsoh 1475 lvds output differential voltage (1, 2, 4) |v od |250 400 lvds output offset voltage (1, 3, 4) v os 1125 1275 mv clock output rise and fall time (5) t r , t f 400 ps lvcmos output voltage low v lvcmosol 400 mv lvcmos output voltage high v l vcmosoh 2500 lvcmos input current high/low i lvcmosi ? 500 500 a lvcmos output current high (6) i lvcmosoh 0.5 ma lvcmos output current low (7) i lvcmosol 4.0 data rate per chan- nel (output) d r 150 500 mbit/s clock frequency sci mode f clock 75 250 mhz clock frequency strobe mode f clock 150 500 mhz mv 1475 925 time |v od |
fiber optics v23814/15-k1306-m230 parallel optical link: paroli ? tx/rx dc 9 notes optical parameters valid for each channel. 1. ber=10 ? 12 at infinite er. this means that the sensitivity specifica- tion equals -13.7 dbm for an input signal with an er of 5 db. 2. p fda : average optical power when frame_det switches from low to high. p fdd : average optical power when frame_det switches from high to low. values are also applicable for sd11 function, except sd11 is low active. figure 10. timing diagrams strobe mode sci mode in this operation mode the clock output is supplied in phase to data outputs. note 1. all data outputs and clock output. frame_det and -reset timing diagrams notes 1. timing also applicable for sd11 function on fiber #12. 2. stable frame input required. -reset not activated. 3. except when used as power-on reset. at any failure recovery, -reset should be brought to low level for at least t 3 . 4. valid if -reset is set high when v cc exceeds 3.0 v level and optical frame (frame_det=high) and data input are valid. t 5 starts when all these conditions are fulfilled. -reset must be set to low during power-up. parameter symbol min. max. units sensitivity (average power) ( 1) p in ? 16.5 dbm saturation (average power) p sat ? 6.0 frame detect assert level ( 2) p fda ? 18.0 frame detect deassert level ( 2) p fdd ? 28.0 frame detect hysteresis ( 2) p fda ? p fdd 1.0 4.0 db return loss of receiver a rl 12 parameter symbol min. typ. max. units output setup time t 1 625 ps output hold time t 2 parameter symbol min. typ. max. units output skew (1) t s 810 ps t 1 t 2 data in 1...22 clock out p n |v od | min. t s t s data out 1...22 clock out p n |v od | min. parameter sym- bol min. max. units frame_det deassert time (1) t 1 10 s frame_det assert time (1) t 2 frame_det low to lock_det low delay t 3 20 ns frame_det high to lock_det high duration (2) t 4 50 ms -reset low duration (3) t 5 100 s -reset off delay time t 6 20 ns -reset on delay time (4) t 7 50 ms lvds output disable time t 8 20 ns lvds output enable time t 9 20 0.4 v optical frame input frame_det 2.5 v lock_det t 1 t 2 t 3 t 4 t 6 t 7 -reset data and clock out valid 2.0 v 0.8 v data low clock low valid t 5 t 8 t 9 oe data and clock out valid 2.0 v 0.8 v data low clock low valid
fiber optics v23814/15-k1306-m230 parallel optical link: paroli ? tx/rx dc 10 figure 11. measurement conventions for lvds signals setup and hold times setup and hold times are measured between the cross point of positive and negative clock and the points where rising and fall- ing data edge cross the borders of the v-range. figure 12. numbering conventions receiver the numbering conventions for the tx and rx modules are the same. receiver pin description pin# pin name level/logic description 1v ee ground 2v cc1 power supply voltage of preamplifier 3v cc2 power supply voltage of analog circuitry 4 t.b.l.o. to be left open 5 -reset lvcmos in low active high=receiver is active. low=internal logic is reset and lvds outputs are set to low. internal pull- up pulls to high level when this input is left open. 6frame_ det lvcmos out high=frame input signal present (on fiber #1) low=insufficient frame signal. this output can be used for connection with an open fi- ber control (ofc) circuit to con- figure an iec class 1 link 7v cc3 power supply voltage of digital circuitry 8v ee ground 9v cc4 power supply voltage of decoder 10 lock_ det lvcmos out high=pll has successfully locked onto incoming frame signal. lock_det being low sets all lvds data outputs to low; clock output is unaffected by lock_det. 11 cop lvds out clock output, non-inverted 12 con lvds out clock output, inverted t setup t hold data clock p n |v od | min. 13 do01p lvds out data output #1, non-inverted 14 do01n lvds out data output #1, inverted 15 do12p lvds out data output #12, non-inverted 16 do12n lvds out data output #12, inverted 17 do02p lvds out data output #2, non-inverted 18 do02n lvds out data output #2,inverted 19 do13p lvds out data output #13, non-inverted 20 do13n lvds out data output #13, inverted 21 do03p lvds out data output #3, non-inverted 22 do03n lvds out data output #3, inverted 23 do14p lvds out data output #14, non-inverted 24 do14n lvds out data output #14, inverted 25 v cc4 power supply voltage of decoder 26 do04p lvds out data output #4, non-inverted 27 do04n lvds out data output #4, inverted 28 v ee ground 29 do15p lvds out data output #15, non-inverted 30 do15n lvds out data output #15, inverted 31 do05p lvds out data output #5, non-inverted 32 do05n lvds out data output #5, inverted 33 do16p lvds out data output #16, non-inverted 34 do16n lvds out data output #16, inverted 35 do06p lvds out data output #6, non-inverted 36 do06n lvds out data output #6, inverted 37 do17p lvds out data output #17, non-inverted 38 do17n lvds out data output #17, inverted 39 do07p lvds out data output #7, non-inverted 40 do07n lvds out data output #7, inverted 41 do18p lvds out data output #18, non-inverted 42 do18n lvds out data output #18, inverted 43 do08p lvds out data output #8, non-inverted 44 do08n lvds out data output #8, inverted 45 v ee ground 46 do19p lvds out data output #19, non-inverted 47 do19n lvds out data output #19, inverted 48 v cc4 power supply voltage of decoder 49 do09p lvds out data output #9, non-inverted 50 do09n lvds out data output #9, inverted 51 do20p lvds out data output #20, non-inverted 52 do20n lvds out data output #20, inverted 53 do10p lvds out data output #10, non-inverted 54 do10n lvds out data output #10, inverted 55 do21p lvds out data output #21, non-inverted 56 do21n lvds out data output #21, inverted 57 do11p lvds out data output #11, non-inverted 58 do11n lvds out data output #11, inverted pin# pin name level/logic description
fiber optics v23814/15-k1306-m230 parallel optical link: paroli ? tx/rx dc 11 optical port designed for the simplex mt connector (smc) port outside dimensions: 15.4 mm x 6.8 mm (width x height) mt compatible (iec 61754-5) fiber spacing (250 m) and alignment pin spacing (4600 m) alignment pins fixed in module port integrated mechanical keying process plug (smc dimensions) included with every module cleaning of port and connector interfaces necessary prior to mating features of the simplex mt connector (smc) (as part of optional paroli fiber optic cables) uses standardized mt ferrule (iec 61754-5) mt compatible fiber spacing (250 m) and alignment pin spacing (4600 m) snap-in mechanism ferrule bearing spring loaded integrated mechanical keying assembly on the next pages are some figures to assist the customer in designing his printed circuit board (pcb). figure 13 shows the mechanical dimensions of the paroli transmitter and receiver modules and figures 14 to 16 give the dimensions of the holes and solder pads on a customer pcb that are necessary to mount the modules on this pcb. keeping the tolerances for the pcb given in figures 14 to 16 is required to properly attach the paroli transmitter and receiver module to the pcb. attachment to the customer pcb should be done with four m2 screws torqued to 0.25 nm + 0.05 nm (see figure 13, cross section b-b). the screw length a should be 3 to 4 mm plus the thickness b of the customer pcb. special care must be taken to remove residues from the solder- ing and washing process which can impact the mechanical function. avoid the use of aggressive organic solvents like ketones, ethers, etc. consult the supplier of the paroli mod- ules and the supplier of the solder paste and flux for recom- mended cleaning solvents. the following common cleaning solvents will not affect the module: deionized water, ethanol, and isopropyl alcohol. air-dry- ing is recommended to a maximum temperature of 150 c. do not use ultrasonics. during soldering, heat must be applied to the leads only, to ensure that the case temperature never exceeds 150 c. the module must be mounted with a hot-air or hot-bar soldering process using a snpb solder type, e.g. sn62pb36ag2, in accor- dance with iso 9435. 59 do22p lvds out data output #22, non-inverted 60 do22n lvds out data output #22, inverted 61 clk_sel lvcmos in input clocking mode select high=strobe mode low=sci mode this input has an internal pull- up resistor. when left open, strobe mode is active. 62 oe lvcmos in high=enable lvds outputs low=set lvds outputs (data and clock) to static low level. in- ternal pull-up pulls to high level when input is left open 63 t.b.l.o. to be left open 64 v cc4 power supply voltage of decoder 65 v ee ground 66 v cc3 power supply voltage of digital circuitry 67 -sd11 lvcmos out low active signal detect optical data channel 11 (on fiber #12) low=signal of sufficient ac power is present on fiber # 12 high=signal on fiber # 12 is in- sufficient. this output can be used for connection with an open fiber control (ofc) cir- cuit to configure an iec class 1 link 68 ensd lvcmos in enable signal detect high=sd11 and frame_det function enabled. low=frame_det and sd11 is set to permanent active. pll is then forced to start lock-on procedure (for test purposes). internal pull-up pulls to high lev- el when input is left open. 69 t.b.l.o. to be left open 70 v cc2 power supply voltage of analog circuitry 71 v cc1 power supply voltage of preamplifier 72 v ee ground pin# pin name level/logic description
fiber optics v23814/15-k1306-m230 parallel optical link: paroli ? tx/rx dc 12 figure 13. drawing of the paroli transmitter and receiver module
fiber optics v23814/15-k1306-m230 parallel optical link: paroli ? tx/rx dc 13 figure 14. recommended circuit board layout: transmitter figure 15. recommended circuit board layout: receiver no electronic components are allowed on the customer pcb within the area covered by the paroli module and the jumper used to attach a ribbon fiber cable. figure 16. mounting hole, detail y
published by infineon technologies ag ? infineon technologies ag 2000 all rights reserved attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact the infineon technologies offices or our infineon technologies representatives worldwide - see our web page at www.infineon.com/fiberoptics warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your infineon technologies offices. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. infineon technologies ag fiber optics wernerwerkdamm 16 berlin d-13623, germany infineon technologies, inc. fiber optics 1730 north first street san jose, ca 95112, usa infineon technologies k.k. fiber optics takanawa park tower 20-14, higashi-gotanda, 3-chome, shinagawa-ku to ky o 14 1, j a p a n figure 17. applications point-to-point tx module ribbon cable lvds rx module paroli smc port lvds smc port paroli i/o board passive optical backplane tx rx feed through optical backplane paroli tx module ribbon cables link controller lvds paroli rx module board-to-board smc port

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